According to a leak from Moore’s Law is Dead, AMD aims to achieve a considerable rise in the number of CPU cores with their forthcoming Ryzen chipsets. With a 50% increase in CPU cores per CCD, the Ryzen 9 models could potentially offer 24 cores total, assuming AMD maintains its typical dual-CCD Ryzen 9 architecture.
These new 12-core Zen 6 CCD CPUs are expected to be integrated across AMD’s entire next-gen CPU portfolio. This design will be utilized in AMD’s future EPYC (Venice) processors, as well as their Medusa Point/Medusa Halo mobile lineups. This strategy allows AMD to apply their Zen 6 CCD design across a wider array of chips, boosting production capabilities while reducing overall chip development expenses.
AMD is anticipated to employ TSMC’s 3nm fabrication process for manufacturing these 12-core Zen 6 CPU CCDs. The amount of cache these CCDs will have remains uncertain. If AMD chooses to maintain 4MB of L3 cache per core, the new 12-core CCDs would encompass 48MB of L3 cache (excluding V-Cache), marking a 50% increase from the 8-core Zen 5 CCDs. However, this heightened cache volume is purely speculative, as AMD might take a different path with their Zen 6 CPU offerings.
As previous leaks have indicated, AMD’s Zen 6 CPU chips will feature a revised interconnect design between CPU CCDs and IO dies. According to Moore’s Law is Dead’s source, AMD plans to implement a silicon interposer, facilitating a higher bandwidth and lower latency interconnect for users. This should reduce memory latencies, enhance inter-CCD bandwidth, and contribute to improved performance for the Zen 6 CPUs.
With the introduction of 12-core CCDs, AMD’s next-generation Ryzen processors are likely to showcase elevated core counts. This will significantly enhance AMD’s multi-threaded performance. Furthermore, the new interconnects should also help optimize the performance of AMD’s dual-CCD processors. Reduced latencies and increased inter-chip bandwidth will help mitigate performance challenges that multi-CCD AMD CPUs face in certain workloads.
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